In stacked silicon interconnect technology (SSIT) devices, adjacent semiconductor dies (e.g., FPGA dies) are connected through an interposer. Each semiconductor die may have its own separate functionality, and semiconductor dies making up the SSIT device may be coupled together through the interposer. Electrical connections between semiconductor dies and interposer are formed using bumps (e.g., microbumps) that are very close in proximity (e.g., 45 μm between bumps).
Assembly of semiconductor dies and the interposer is typically performed at a wafer level. In other words, processing of several interposer dies making up an interposer wafer may be performed together for assembly of those interposer dies with corresponding semiconductor dies. The interposer wafer may include several complete interposer die as well as incomplete interposer die (e.g., edge dies). The complete interposer dies that have been tested and meet a standard of quality (e.g., good interposer dies) are populated with semiconductor dies, while incomplete dies (e.g., edge dies) and defective complete dies (e.g., bad interposer dies) are not populated with semiconductor dies.
During fabrication of the interposer wafer, bumps are formed on the entirety of the interposer wafer, including incomplete interposer dies and defective interposer dies. This is done in order to ensure bump uniformity and optimal bump density across the wafer and to promote effective current density, among other reasons. However, not all of the bumps formed on the interposer wafer are used to populate interposer dies or defective interposer dies are not populated with semiconductor dies and may become dislodged and trapped between bumps used to populate semiconductor dies, causing shorts and other reliability problems.